This invention relates to providing high-availability parallel processing super servers.
The present invention provides a high-availability parallel processing server that is a multi-processor computer with a segmented memory architecture. The processors are grouped into processor clusters, with each cluster consisting of up to four processors in a preferred embodiment, and there may be up to 5 clusters of processors in a preferred embodiment. Each cluster of processors has dedicated memory buses for communicating with each of the memory segments. The invention is designed to be able to maintain coherent interaction between all processors and memory segments within a preferred embodiment. A preferred embodiment uses Intel Pentium-Pro processors (hereinafter P6). The invention may be modified to utilize other processors, such as those produced by AMD or CYRIX. (Registered trademarks referenced herein belong to their respective owners.)
The present invention comprises a plurality of processor segments (a cluster of one or more CPUs), memory segments (separate regions of memory), and memory communication buses (pathways to communicate with the memory segment). Each processor segment has a dedicated communication bus for interacting with each memory segment, allowing different processors parallel access to different memory segments while working in parallel.
The processors, in a preferred embodiment, may further include an internal cache and flags associated with the cache to indicate when the data within the cache may be out of date, or if the data within the cache is data shared by other processors within the invention. Through use of setting the internal cache flag to a desired state, the contents of the internal cache of a processor may be effectively monitored from a vantage point external to the processor. This would allow for maintaining multi-processor cache coherency without requiring all processors to observe all other processors memory traffic.
The processors, in a preferred embodiment, may further comprise processors with caches external to the processor, where such cache may be an external write-back cache. There may also be caches associated with the memory communication buses to allow for enhanced memory access. In a preferred embodiment utilizing P6 processors, the processors may also be configured to operate in clusters of up to four processors to a processor segment. Note that this four processor limitation is one due to the P6 architecture. If an alternate processor is used, in which the alternate processor design allows more than four processors to a bus, then cluster size referenced herein may be adjusted accordingly.